Fachbeitrag Making Motor Drives smarter

The use of variable speed drives (VSDs) in motor-driven systems provides significant energy savings, but VSDs require complex control algorithms that can be limited by off-the-shelf microcontrollers or digital signal processors, particularly when combined with the requirement for other services like networking and safety. Designers are now turning to FPGAs for next generation VSD systems because of their inherent flexibility, performance and system integration. FPGAs can integrate most of the building blocks of a motor control system, processing the control loops and system management in parallel. Soft processors can manage the system and implement Industrial Ethernet protocols such as EtherCAT or Profinet, whereas the FPGA logic can handle the time-critical motor algorithms such as Field Oriented Control (FOC) in either fixed or floating point. However, motor control engineers are skilled in software or DSP algorithms, but are not familiar with FPGA or RTL design. Model-based DSP development environments (e.g. Matlab/Simulink) combined with block based tools, such as Altera�??s DSP Builder Advanced Blockset, enable DSP designers to work in a productive and familiar environment and to automatically generate optimized RTL. The use of FPGAs allows higher throughput and processing rates because of the parallelism of the hardware. Lower latency can be achieved due to hardware acceleration of tasks and a direct interface between the control loop algorithm and the sensor interface. A high-level design synthesis from Simulink directly to the FPGA implementation with the ability to automatically trade off latency, throughput and resource usage can be realized. In a typical FOC controller the inputs are sampled at 10 - 100 ksps. At 100 ksps a new sample must be processed in less than 10 µs. Simultaneously keeping processing latency constant and to a minimum are beneficial to the performance of the control algorithm. Floating-point implementation delivers the elimination of arithmetic overflow and scaling issues, a superior performance due to inherently greater numerical stability and potentially more rapid control loop responses due the high dynamic range. FPGAs can support both fixed and floating-point solutions, and can easily deliver 200k loops or PWM outputs a second. Size optimization reduces the FPGA resources by a factor of ~4 at a cost of a 65 per cent increase in latency (still ten times faster than the 100 ksps required for FOC). Through this resource optimization floating point and multi-axis control implementations in one low cost device become an achievable target. As a result FPGAs are the perfect motion control platform for VSDs of tomorrow.

FPGA for motor control

The use of FPGAs for motor control brings a lot of advantages for designers. The implementation of floating point on the one hand leads to higher performance, which means on the other hand that less FPGA resources are necessary, so the costs can be reduced significantly. The integration of tools like Matlab, Simulink and Altera�??s DSP builder into the design flow does not only facilitate the work for the designer, but also leads to an optimized FPGA design. And the integration of digital encoder interfaces and any industrial Ethernet protocol brings the flexibility that is needed for VSDs to succeed everywhere.